ISTFA 2006

ISTFA 2006

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A block diagram of the test chip design is shown in Fig. 1a. ... (FFs) connected in a scan chain configuration, a shorting inverter, and a defect emulation transistor connected to a globally routed defect emulation wire. Fig. 1b shows a schematic diagram of two adjacent TCs. ... The first type shorts the power grid to ground through the inverter using FF1 and FF2; the second type shorts the power grid to theanbsp;...

Title:ISTFA 2006
Author: Electronic Device Failure Analysis Society, ASM International
Publisher:ASM International - 2006

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